1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for an interpoly dielectric layer.
2. Background of the Invention
Flash memory is an electrically erasable and programmable read-only memory (EEPROM) that is widely used in computer and microprocessor systems for permanently storing information that are repeatedly read, written or erased. Moreover, flash memory can retain information even when power is interrupted. Flash memory is a type of non-volatile memory (NVM), which is small in size, faster in reading/programming speed and consumes less power and energy. Since the erasure of information for a flash memory is accomplished xe2x80x9cblock-by-blockxe2x80x9d, the operational speed is also faster.
FIGS. 1A to 1C are schematic diagrams in cross-sectional views illustrating the fabrication of a flash memory device according to the prior art.
As shown in FIG. 1A, a substrate 100 is provided, wherein a tunnel oxide layer 102 is formed on the substrate 100. A patterned polysilicon layer 104, serving as a floating gate, is formed on the tunnel oxide layer 102. A buried drain region 106 is then formed in the substrate 100 beside the side of the polysilicon layer 104.
Referring to FIGS. 1B to 1C, a dielectric layer 108 is formed on the substrate 100. After this, another polysilicon layer 110, serving as the control gate, is formed on the dielectric layer 108 that is on the polysilicon layer 104.
The dielectric layer 108 is formed by, for example, a thermal process. The thermal process is conducted at a temperature of about 900 degrees Celsius in an oxygen environment to induce a reaction between the oxygen molecules and the silicon atoms of the polysilicon layer 104 to form an oxide type of dielectric layer 108. However, the surface of the dielectric layer 108 formed by the conventional thermal process is rough. A rough surface would cause a current leakage between the two polysilicon layers 104, 110. Moreover, the dielectric layer 108 that is formed by the conventional thermal process is at a temperature of about 900 degrees Celsius. Under such a high temperature, the dopants of the buried drain region 106 in the substrate 100 would diffuse into the tunnel oxide layer 102, causing a current leakage.
Additionally, in the conventional approach, in order to increase the sustainability to high electric field, a silicon oxide-silicon nitride-silicon oxide (ONO) stacked layer or an silicon oxide-silicon nitride (ON) stacked layer is used as the interpoly dielectric layer 108 for the flash memory device. However, forming the ONO stacked layer or the ON stacked layer requires multiple process steps greatly increases the complexity of the manufacturing process.
The present invention provides a fabrication method for an interpoly dielectric layer, wherein an interpoly dielectric layer having a rough surface formed by the conventional thermal process is prevented.
The present invention also provides a fabrication method for an interpoly dielectric layer, wherein the problem encountered in forming an interpoly dielectric layer that can sustains a higher electric field as in the prior art is prevented.
The prevent invention further provides a fabrication method for a flash memory device, wherein the diffusion of dopants from the buried drain in the substrate to the tunnel oxide layer due to the high temperature in forming the interpoly dielectric layer is prevented.
The present invention additionally provides a fabrication method for an interpoly dielectric layer of a flash memory device in which current leakage is reduced to increase the reliability of the device.
The present invention provides a fabrication method for an interpoly dielectric layer, wherein the method provides a substrate having a first polysilicon layer already formed thereon. An interpoly dielectric layer is then formed on the first polysilicon layer. The interpoly dielectric layer is formed under a temperature of about 400 degrees Celsius, using an argon gas/oxygen gas/ammonia gas plasma, a krypton gas/oxygen gas/ammonia gas plasma, an argon gas/oxygen gas plasma or a krypton gas/oxygen gas plasma. The composition ratio of argon gas to oxygen gas to ammonia gas in the argon gas/oxygen gas/ammonia gas plasma is 96.5:3:0.5. The composition ratio of krypton gas to oxygen gas to ammonia gas in the krypton gas/oxygen gas/ammonia gas plasma is about 96.5:3:0.5. The composition ratio of argon gas to oxygen gas in the argon gas/oxygen gas plasma is 97:3. The composition ratio of krypton gas to oxygen gas in the krypton gas/oxygen gas plasma is 97:3.
The present invention provides a fabrication method for a flash memory device. This method provides a substrate, and a tunnel oxide layer is formed on the surface of the substrate. A patterned first polysilicon layer is then formed on the tunnel oxide layer as the floating gate. A buried drain region is the formed in the substrate beside the first polysilicon layer. A dielectric layer is then formed on the first polysilicon layer as the interpoly dielectric layer, wherein the dielectric layer is formed at a temperature of about 400 degrees Celsius using an argon gas/oxygen gas/ammonia gas plasma, a krypton gas/oxygen gas/ammonia gas plasma, an argon gas/oxygen gas plasma or a krypton gas/oxygen gas plasma. The composition ratio of argon gas to oxygen gas to ammonia gas in the argon gas/oxygen gas/ammonia gas plasma is 96.5:3:0.5. The composition ratio of krypton gas to oxygen gas to ammonia gas in the krypton gas/oxygen gas/ammonia gas plasma is about 96.5:3:0.5. The composition ratio of argon gas to oxygen gas in the argon gas/oxygen gas plasma is 97:3. The composition ratio of krypton gas to oxygen gas in the krypton gas/oxygen gas plasma is 97:3. A second polysilicon layer is then formed on the dielectric layer as the control gate.
In accordance of the fabrication method for an interpoly dielectric layer of the present invention, the oxygen ions in the plasma exhibits no lattice orientation dependency, the interpoly dielectric layer is thus more uniformly formed.
According to the fabrication method for an interpoly dielectric layer of the present invention, the oxygen ions in the plasma is smaller in size and thus diffuse faster through the polyoxide growing film to react with the silicon atoms to form the interpoly dielectric layer. The growing of the inter-poly dielectric layer to the desired thickness can thus be faster and at a lower temperature.
According to the present invention, only a single process step is required to obtain an interpoly dielectric layer that is sustainable to high electric field. The complexity of the manufacturing process is thereby reduced.
According to the fabrication method for a flash memory device of the present invention, the interpoly dielectric layer is formed at a temperature of about only 400 degrees Celsius. A diffusion of dopants from the buried doped drain in the substrate to the tunnel oxide layer is thus obviated.
The interpoly dielectric layer of a flash memory device formed according to the present invention reduces the occurrences of a current leakage to increase the reliability of a device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.